The continued development and proliferation of digital technology results in large quantities of digital data being generated, transmitted, collected, processed, and stored. For example, in processing a large quantity of information, such as a data stream from a satellite, conversion of raw data by a fast analog-to-digital converter may generate a large stream of digital data. In order to accommodate the large stream of digital data, the stream may be deserialized into multiple separate streams of data that can be stored or processed by available digital devices.
One way of deserializing a large digital data stream is to demultiplex the data stream with the demultiplexed outputs routed to separate digital devices or to separate inputs of a digital system. However, demultiplexing the digital data stream presents its own problems.
For example, if the analog-to-digital converter has an eight bit output and the output is to be divided into eight separate streams to accommodate the data, an 8-bit-to-64-bit (8:64) demultiplexer may be used. However, inexpensive 8:64 demultiplexers generally may not be commercially available. Further, an 8:64 demultiplexer is a relatively high density device and relatively few 8:64 demultiplexers may be manufactured on a single wafer which may lead to wafer yield concerns. By contrast, lower density demultiplexers, such as 1:8 or 2:16 demultiplexers may be commonly commercially available and may have higher wafer yields leading to reduced costs.
Although an 8:64 demultiplexer may be replaced by an array of individual demultiplexers, such as an array of four parallel 2:16 demultiplexers or an array of eight parallel 1:8 demultiplexers, a problem remains in synchronizing the individual demultiplexers. The individual demultiplexers may each include a data tree and a clock divider that accepts a reference clock input and clocks a demultiplexed data output at a reduced clock rate. However, as is the case with many digital devices, on being powered up, different demultiplexers may start up with different gates in different states. As a result, the individual demultiplexers may start up with their respective clock dividers in different states, resulting in the output of the different individual demultiplexers being out of synchronization and potentially causing misalignment of the deserialized data bits in the output.
Some demultiplexers and other digital devices may be equipped with clock reset inputs. However, applying an accurately synchronized input to each of a plurality clock inputs may be difficult. Further, if a clock reset input fails to properly reset a clock divider or if the clock reset signal is not accurately and simultaneously applied to each of the devices, the devices may remain desynchronized as long as the devices remain powered on.